STR-DN860/DN1060
104
MB-1409 BOARD (11/18) IC3002 MB9BF129TPMC-GE1 (SYSTEM CONTROLLER)
Pin No. Pin Name I/O Description
1 VCC - Power supply pin (+3.3V)
2 ADV8003_SPSF_DIN I ADV8003 SPI SOMI
3
ADV8003_SPSF_
DOUT
O ADV8003 SPI SIMO
4 ADV8003_SPSF_SCK O ADV8003 SPI SCK
5
ADV8003_P_
CONT_1.8V
O HDMI ADV 18V CONT
6 ADV8003_RESET O ADV8003 RESET signal output terminal
7 ADV8003_SPI_CS O ADV8003 Chip Select
8 TEST1 O Test Pad 1 (for designer evaluation only)
9 TEST2 O Test Pad 2 (for designer evaluation only)
10 TEST3 O Test Pad 3 (for designer evaluation only)
11 TEST4 O Test Pad 4 (for designer evaluation only)
12 TEST5 O Test Pad 5 (for designer evaluation only)
13 ADV8003_INT0 I ADV8003 INTerrupt port 0
14 ADV8003_INT1 I ADV8003 INTerrupt port 1
15 ADV8003_INT2 I ADV8003 INTerrupt port 2
16 ADV8003_P_DOWN O ADV8003 POWER DOWN
17 SWSEL_A O HDMI Switcher 5V Power Select
18 SWSEL_B O HDMI Switcher 5V Power Select
19 CEC_IN_OUT I/O CEC Input/Output Peripheral
20 E2P_SDA I/O Two-way data bus with the EEPROM
21 E2P_SCL O Serial data transfer clock signal output to the EEPROM
22 HDMI_CECIN - CEC Serial data input from the HDMI connector (Not Used)
23 HDMI_CECOUT - CEC serial data output to the HDMI connector (No Used)
24 CEC_PCONT O Control the CEC relay at HDMI out terminal.
25 TEST_6 O Test Pad 6 (for designer evaluation only)
26 TEST_7 O Test Pad 7 (for designer evaluation only)
27 VSS - Ground terminal
28 TEST_8 O Test Pad 8 (for designer evaluation only)
29 BD_SCL(IF_SCK) I Serial data transfer clock signal input from MT8506
30 BD_SDI(IF_SDO) O Serial data output to MT8506
31 BD_SDO(IF_SDI) I Serial data input from MT8506
32 BD_CS(XIF_CS) O Chip select signal output to MT8506
33
WOL_WLAN(WOL_
INT)
I WOL (wake-on-LAN) wake-up signal input from MT8506 “H”:wake-up
34
BD_IF_START(START_
BIT)
O Ready signal output to MT8506 “H”:ready
35 BD_REQ(SYS_REQ) I Request signal input from MT8506 “H”: request
36
BD_RESET(CPU_
XRST)
O Reset signal output to MT8506 “L”: reset
37
JIG_MODE1(EXT_JIG_
MODE1)
I/O
This port is Jig mode selection signal OUTPUT to MT8506.
(Normal case this port is input. Output LOW when USB update start by FLD. )
38 OPWRSB I Power control signal input from the BD decoder
39 UPG_STATUS I UPG signal input from MT8506
40
PCONT_WOL_STAND-
BY
O Wake On Lan Power Control
41 NAND_RESET O Reset signal output to the NAND fl ash “L”: reset
42 MTK_ZONE2_MUTE O MTK ZONE2 DAC MUTE
43 MTK_ZONE2_RST O MTK ZONE2 DAC RESET
44 VSS - Ground Terminal
45 VCC - Power supply pin (+3.3V)
46 SIRCS_IN I SIRCS signal input
47 HP_DET I Headphone Detection signal input
48 NC - Not used
49 FL_ENABLE O Enable control for FL DISPLAY DRIVER IC
50 FL_BK O Blanking period signal output to the fl uorescent indicator tube
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