Debug management AN3320
18/29 Doc ID 18267 Rev 2
4 Debug management
4.1 Introduction
The Host/Target interface is the hardware equipment that connects the host to the
application board. This interface is made of three components: a hardware debug tool, a
JTAG or SW connector and a cable connecting the host to the debug tool.
Figure 11 shows the connection of the host to the evaluation board STM3220G-EVAL.
Figure 11. Host-to-board connection
4.2 SWJ debug port (serial wire and JTAG)
The STM32F20xxx/21xxx core integrates the serial wire / JTAG debug port (SWJ-DP). It is
an ARM® standard CoreSight™ debug port that combines a JTAG-DP (5-pin) interface and
a SW-DP (2-pin) interface.
● The JTAG debug port (JTAG-DP) provides a 5-pin standard JTAG interface to the AHP-
AP port
● The serial wire debug port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG
pins of the JTAG-DP.
4.3 Pinout and debug port pins
The STM32F20xxx/21xxx MCU is offered in various packages with different numbers of
available pins. As a result, some functionality related to the pin availability may differ from
one package to another.
4.3.1 SWJ debug port pins
Five pins are used as outputs for the SWJ-DP as alternate functions of general-purpose
I/Os (GPIOs). These pins, shown in Tab l e 2 , are available on all packages.
%VALUATIONBOARD
(OST0#
0OWERSUPPLY
*4!'37CONNECTOR
$EBUGTOOL
AIB
To Next Page
Loading...
Need help?
General
