Power supplies AN3320
8/29 Doc ID 18267 Rev 2
1.2 Power supply schemes
The circuit is powered by a stabilized power supply, V
DD
.
● Caution:
– The V
DD
voltage range is 1.8 V to 3.6 V (and 1.65 V to 3.6 V for WLCSP64+2
package)
● The V
DD
pins must be connected to V
DD
with external decoupling capacitors: one
single Tantalum or Ceramic capacitor (min. 4.7 µF typ.10 µF) for the package + one
100 nF Ceramic capacitor for each V
DD
pin.
● The V
BAT
pin can be connected to the external battery (1.65 V < V
BAT
< 3.6 V). If no
external battery is used, it is recommended to connect this pin to V
DD
with a 100 nF
external ceramic decoupling capacitor.
● The V
DDA
pin must be connected to two external decoupling capacitors (100 nF
Ceramic + 1 µF Tantalum or Ceramic).
● The V
REF+
pin can be connected to the V
DDA
external power supply. If a separate,
external reference voltage is applied on V
REF+
, a 100 nF and a 1 µF capacitors must be
connected on this pin. In all cases, V
REF+
must be kept between 1.65 V and V
DDA
.
● Additional precautions can be taken to filter analog noise:
–V
DDA
can be connected to V
DD
through a ferrite bead.
–The V
REF+
pin can be connected to V
DDA
through a resistor (typ. 47 Ω).
● For the voltage regulator configuration, there are specific pins (REGOFF and IRROFF
depending on the package) that should be connected either to VSS or VDD to activate
or deactivate the voltage regulator specific. Refer to section "Voltage regulator" in
STM32F20xxx/21xxx datasheet for details.
● When the voltage regulator is enabled, V
CAP1
and V
CAP2
pins must be connected to
2*2.2 µF Ceramic capacitor.
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