AN3320 Reference design
Doc ID 18267 Rev 2 23/29
6 Reference design
6.1 Description
The reference design shown in Figure 14, is based on the STM32F207IF(H6), a highly
integrated microcontroller running at 120 MHz, that combines the Cortex
™
-M3 32-bit RISC
CPU core with 1 Mbyte of embedded Flash memory and up to 128 + 4 Kbytes of high-speed
SRAM
.
This reference design can be tailored to any other STM32F20xxx/21xxx device with different
package, using the pins correspondence given in Table 6: Reference connection for all
packages.
6.1.1 Clock
Two clock sources are used for the microcontroller:
● LSE: X1– 32.768 kHz crystal for the embedded RTC
● HSE: X2– 25 MHz crystal for the STM32F20xxx/21xxx microcontroller
Refer to Section 2: Clocks on page 12.
6.1.2 Reset
The reset signal in Figure 14 is active low. The reset sources include:
● Reset button (B1)
● Debugging tools via the connector CN1
Refer to Section 1.3: Reset & power supply supervisor on page 9.
6.1.3 Boot mode
The boot option is configured by setting switches SW2 (Boot 0) and SW1 (Boot 1). Refer to
Section 3: Boot configuration on page 16.
Note: In low-power mode (more specially in Standby mode) the boot mode is mandatory to be
able to connect to tools (the device should boot from the SRAM).
6.1.4 SWJ interface
The reference design shows the connection between the STM32F20xxx/21xxx and a
standard JTAG connector. Refer to Section 4: Debug management on page 18.
Note: It is recommended to connect the reset pins so as to be able to reset the application from
the tools.
6.1.5 Power supply
Refer to Section 1: Power supplies on page 6.
To Next Page
Loading...
Need help?
General
