ST STM32F20 Series User Manual

Debug management AN3320
20/29 Doc ID 18267 Rev 2
To avoid any uncontrolled I/O levels, the STM32F20xxx/21xxx embeds internal pull-up and
pull-down resistors on JTAG input pins:
● JNTRST: Internal pull-up
● JTDI: Internal pull-up
● JTMS/SWDIO: Internal pull-up
● TCK/SWCLK: Internal pull-down
Once a JTAG I/O is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
● JNTRST: Input pull-up
● JTDI: Input pull-up
● JTMS/SWDIO: Input pull-up
● JTCK/SWCLK: Input pull-down
● JTDO: Input floating
The software can then use these I/Os as standard GPIOs.
Note: The JTAG IEEE standard recommends to add pull-up resistors on TDI, TMS and nTRST but
there is no special recommendation for TCK. However, for the STM32F20xxx/21xxx, an
integrated pull-down resistor is used for JTCK.
Having embedded pull-up and pull-down resistors removes the need to add external
resistors.
4.3.4 SWJ debug port connection with standard JTAG connector
Figure 12 shows the connection between the STM32F20xxx/21xxx and a standard JTAG
connector.
Figure 12. JTAG connector implementation
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ST STM32F20 Series Specifications

General

Brand	ST
Model	STM32F20 Series
Category	Microcontrollers
Language	English

Summary

Power Supplies

Voltage Regulator Operation

Explains the embedded voltage regulator and its operating modes.

Power Supply Schemes and Decoupling

Describes recommended external power supply connections and decoupling.

Reset and Power Supply Supervision

Power-On/Power-Down Reset (POR/PDR)

Details the integrated POR/PDR circuitry and its operation.

Programmable Voltage Detector (PVD)

Explains the PVD for monitoring VDD supply and generating interrupts.

System Reset Sources

Clock Management

HSE Oscillator Clock

LSE Oscillator Clock

Clock Security System (CSS)

Explains the CSS for detecting HSE oscillator failures.

Boot Configuration

Boot Mode Selection Methods

How to select boot modes using BOOT pins.

Boot Pin External Connections

Embedded Boot Loader Mode

Describes the embedded boot loader for Flash memory reprogramming.

Debug Management

SWJ Debug Port (Serial Wire & JTAG)

Explains the integrated SWJ-DP port combining JTAG and SW modes.

Debug Port Pinout and Availability

SWJ Debug Port Pin Configuration

Identifies the specific pins used for SWJ-DP functionality.

Flexible SWJ-DP Pin Assignment

JTAG Pin Pull-up/Pull-down Resistors

SWJ Debug Port to JTAG Connector

Shows the pin connections for SWJ-DP to a standard JTAG connector.

Design Recommendations

Printed Circuit Board Design

Ground and Power Supply Layout

Decoupling Capacitor Strategy

Recommendations for decoupling capacitors for power supply stability.

Reference Design

Reference Design Overview

Reference Design Component List

Lists mandatory and optional components for the reference design.