Supermicro Supero C7Z97-M - Memory Overclocking

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Supermicro C7Z97-M Series Motherboard User’s Manual
tRDWRDD
This option congures between module read to write delay from
different DIMMs. The default is 20.
RTL (ChA)
This option congures round trip latency for channel A. The default
is 50.
RTL (ChB)
This option congures round trip latency for channel B. The default
is 58.
IO-L (ChA)
This option congures I/O latency for channel A. The default is 5.
IO-L (ChB)
This option congures I/O latency for channel B. The default is 12.
ODT WR (ChA)
This option congures the memory on die termination resistors' WR
for channel A. The default is 60
ODT WR (ChB)
This option congures the memory on die termination resistors' WR
for channel B. The default is 60
ODT NOM (ChA)
This option changes the ODT (CHA) Auto/Manual settings. The de-
fault is 60.
ODT NOM (ChB)
This option changes the ODT (CHB) Auto/Manual settings. The de-
fault is 60.
MRC Fast Boot
This option enable Memory Fast Boot to skip DRAM memory training
for booting faster. The options are Enabled and Disabled.
DIMM Exit Mode
This item species the Exit Mode support options. The options are
Auto, Slow Exit, and Fast Exit.