Theory of Operation
Power (PWR) Board
The PWR board pr
ovides DC power to the fans, HDD, CD Drive, μATX board,
MIO board, and AWG12G board. All the power comes from the CVR460 module.
The fan control circuit has a thermal sensor on this board. DC voltage to the fans
is controlled relative to the sensed temperature. DC-DC converters are included
for generating different DC voltages.
CLK12G Board
The CLK12G board provides a 6 GHz to 12 GHz clock to the AWG12G board.
Two clock outputs go to the CH1 and CH2 DAC. The clock output to CH2 should
be terminated for 1 channel models. The clock input accepts 6 GHz to 12 GHz
clock signals from an external signal source. The reference clock input accepts
10 MHz to 8
00 MHz reference clock signals from an external signal source. The
10 MHz reference output can be used for synchronizing frequency between two or
more instruments. The CLK12G board consists of the following blocks:
YIG oscillator (6 GHz to 12 GHz)
Fractio
nal-N PLL
10.0 MHz TCXO (reference oscillator)
AWG12G
Board
The AWG12G board generates arbitrary waveforms based on the waveform
memory and the sequence memory. There are two types of PLDs (Xilinx FPGA)
on the board. One is an AWG controller called PLD131, which interfaces to/from
the M
IO board. The other is a m emory controller called PLD130 which generates
waveform patterns. Waveform data is stored in ZBT type SRAMs. The sequence
memory is included in the memory controller PLD. The AWG12G board consists
of the following blocks:
12 GS/s DAC (HFD205 ASIC)
8 channels 8:1 MUX (TEK0015 ASIC)
PL
D230 (Xilinx Virtex-4 FPGA) as a memory controller
PLD231 (Xilinx Virtex-4 FPGA) as an AWG controller
ZBT type SRAM for the waveform memory
Inter-channel phase detector
Trigger and event inputs
DC Output
DC-DC converter (1.2 V and 2.5 V power supply)
Dynamic Jump input (AWG7000C Series)
AWG7000B and AWG7000C Series Service Manual 2–7
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