68 CBLé System Guidebook
Miscellaneous Reference Information
(Continued)
Improving Data Collection Accuracy Using Pause
When the sample time specified in
CMD3
is faster than 0.003 seconds,
sample events can be affected by the CBL having to respond to a
Get(
,
GET
or
Input "CBLGET"
instruction from a calculator.
If Record Time is on, discrepancies will be found in the collected data.
This is because the CBL is actively communicating with the calculator
when a
Get(
,
GET
, or
Input "CBLGET"
instruction is executed
immediately after receiving a
Send(
,
Send {
, or
Outpt("CBLSEND"
instruction that contains a
CMD3
.
To ensure that valid sampling and triggering occurs, you should put a
Pause
instruction immediately after a
Send(
,
Send {
or
Outpt("CBLSEND"
instruction when the
Send(
,
Send {
or
Outpt("CBLSEND"
instruction contains a
CMD3
. When sampling is
complete (
DONE
indicator is on), press Í on the calculator to
execute the next instruction of the program.
Clock-In Line Operation
A low-going pulse (5–0 Volts) on the External Clock-In line (part of the
DIG IN
channel) is used for an external clock. This signal is only
recognized as a sample clock when the Sample Time and External Clock
Source parameters in
CMD3
are both set to zero.
Data from the
DIG IN
channel may be read based on the internal
sampling clock, and does not require the use of the External Clock-In
line. Conversely, the External Clock-In line can be used to control the
sampling time for signals on the other channels.
Clock-Out Line Operation
At each sample time, the External Clock-Out line (part of the
DIG OUT
channel) goes low for about 3 microseconds. The digital output lines
change to the next value and are valid when the External Clock-Out line
returns high.
The Clock-Out line provides the low-going 3-microsecond pulse on all
sample events (not just the events associated with
DIG OUT
operation),
except for certain conditions when the sample time is less than 0.00020
seconds. This allows the signal to be used to “slave” additional CBLs by
connecting to their external Clock-In lines. However, care should be
taken to make sure circuits connected to the
DIG OUT
channel are not
confused by these clock pulses if other channels are actively sampled.
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