Texas Instruments TMS320F28069

145
TMS320F28069 , TMS320F28068 , TMS320F28067 , TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
www.ti.com SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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TMS320F28064 TMS320F28063 TMS320F28062
Detailed DescriptionCopyright © 2010–2016, Texas Instruments Incorporated
(1) I = Input, O = Output
Table 6-73. Analog MUX for 100-Pin PZ and 100-Pin PZP Packages
(1)
DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I) ADCINA0 (I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 ADCINA3 (I) ADCINA3 (I)
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 ADCINA5 (I) ADCINA5 (I)
13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I)
15-14 ADCINA7 (I) ADCINA7 (I)
17-16 ADCINB0 (I) ADCINB0 (I)
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 ADCINB3 (I) ADCINB3 (I)
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 ADCINB5 (I) ADCINB5 (I)
29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I)
31-30 ADCINB7 (I) ADCINB7 (I)
(1) I = Input, O = Output
Table 6-74. Analog MUX for 80-Pin PN and 80-Pin PFP Packages
(1)
DEFAULT AT RESET
AIOx AND PERIPHERAL SELECTION 1
PERIPHERAL SELECTION 2 AND
PERIPHERAL SELECTION 3
AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x
1-0 ADCINA0 (I), V
REFHI
(I) ADCINA0 (I), V
REFHI
(I)
3-2 ADCINA1 (I) ADCINA1 (I)
5-4 AIO2 (I/O) ADCINA2 (I), COMP1A (I)
7-6 – –
9-8 AIO4 (I/O) ADCINA4 (I), COMP2A (I)
11-10 ADCINA5 (I) ADCINA5 (I)
13-12 AIO6 (I/O) ADCINA6 (I), COMP3A (I)
15-14 – –
17-16 ADCINB0 (I) ADCINB0 (I)
19-18 ADCINB1 (I) ADCINB1 (I)
21-20 AIO10 (I/O) ADCINB2 (I), COMP1B (I)
23-22 – –
25-24 AIO12 (I/O) ADCINB4 (I), COMP2B (I)
27-26 ADCINB5 (I) ADCINB5 (I)
29-28 AIO14 (I/O) ADCINB6 (I), COMP3B (I)
31-30 – –