47
TMS320F28069
,
TMS320F28068
,
TMS320F28067
,
TMS320F28066
TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062
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SPRS698F –NOVEMBER 2010–REVISED MARCH 2016
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Detailed DescriptionCopyright © 2010–2016, Texas Instruments Incorporated
6.2 Memory Maps
In Figure 6-1 through Figure 6-8, the following apply:
• Memory blocks are not to scale.
• Peripheral Frame 0, Peripheral Frame 1, Peripheral Frame 2, and Peripheral Frame 3 memory maps
are restricted to data memory only. A user program cannot access these memory maps in program
space.
• Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline
order.
• Certain memory ranges are EALLOW protected against spurious writes after configuration.
• Locations 0x3D 7C80–0x3D 7CC0 contain the internal oscillator and ADC calibration routines. These
locations are not programmable by the user.
• All devices with USB have the USB control registers mapped from 0x4000 to 0x4FFF and 2K ×16 RAM
from 0x40000 to 0x40800. When the clock to the USB module is enabled, this RAM is connected to
the USB controller and acts as the FIFO RAM. When the clock to the USB module is disabled, this
RAM is remapped to the CPU-accessible address space and can be used as general-purpose RAM.
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