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6.5.1 CPU Common Options
RedirecForReturnDis
From a workaround for GCC/C000005 issue for XV Core on CA A0,setting
MSRC001_1029 Decode Configuration (DE_CFG) bit 14
[DecfgNoRdrctForReturns] to 1
Auto / 1 / 0
Platform First Error Handling
Enable/disable PFEH, cloak individual banks, and mask deferred error interrupt from
each bank.
Enabled / Disabled / Auto
Core Performance Boost
Disable CPB
Disabled / Auto
Global C-state Control
Controls IO based C-state generation and DF C-states.
Enabled / Disabled / Auto
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