VIA694X System Board 38
SDRAM Cycle Length: control the DRAM page missing and row miss leadoff
timing.
:2
:3 (default)
DRAM Clock
:Host CLK (default)
System shows the actual DRAM speed the system uses.
:HCLK+33M
Please check DRAM clock for optimizes selection.
Memory Hole : this field enable a memory hole in main memory space. CPU
cycles matching an enabled hold are passed on to PCI note that a selected can not
be changed while the L2 cache is enabled.
:Disabled (default)
:15M-16M
P2C/C2P Concurrency
:Enabled (default)
:Disabled
Fast R-W Turn Around
:Enabled
:Disabled (default)
System BIOS Cacheable
:Enabled (default)
:Disabled
Video RAM Cacheable
:Enabled(default) --- allows caching of the video RAM, resulting in better system
performance. However, if any program writes to this memory area, a system error
may occur.
:Disabled
To Next Page
Loading...
Need help?
General
