Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 123
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_CK_C"]
set_property PACKAGE_PIN AE16 [get_ports "DDR4_CK_T"]
set_property IOSTANDARD DIFF_SSTL12_DCI [get_ports "DDR4_CK_T"]
set_property PACKAGE_PIN AD15 [get_ports "DDR4_CKE"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CKE"]
set_property PACKAGE_PIN AH14 [get_ports "DDR4_ACT_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ACT_B"]
set_property PACKAGE_PIN AJ16 [get_ports "DDR4_ALERT_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ALERT_B"]
set_property PACKAGE_PIN AJ18 [get_ports "DDR4_ODT"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_ODT"]
set_property PACKAGE_PIN AD18 [get_ports "DDR4_PAR"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_PAR"]
set_property PACKAGE_PIN AH16 [get_ports "DDR4_TEN"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_TEN"]
set_property PACKAGE_PIN AL19 [get_ports "DDR4_CS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_CS_B"]
set_property PACKAGE_PIN AL18 [get_ports "DDR4_RESET_B"]
set_property IOSTANDARD LVCMOS12 [get_ports "DDR4_RESET_B"]
#FMC HPC
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK0_M2C_N"]
set_property PACKAGE_PIN G12 [get_ports "FMC_HPC_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK0_M2C_P"]
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK0_M2C_P"]
set_property PACKAGE_PIN H12 [get_ports "FMC_HPC_CLK0_M2C_P"]
set_property PACKAGE_PIN D25 [get_ports "FMC_HPC_CLK1_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK1_M2C_N"]
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK1_M2C_N"]
set_property PACKAGE_PIN E25 [get_ports "FMC_HPC_CLK1_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_CLK1_M2C_P"]
set_property DIFF_TERM TRUE [get_ports "FMC_HPC_CLK1_M2C_P"]
set_property PACKAGE_PIN L27 [get_ports "FMC_HPC_PG_M2C_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC_PG_M2C_LS"]
set_property PACKAGE_PIN H24 [get_ports "FMC_HPC_PRSNT_M2C_B_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC_PRSNT_M2C_B_LS"]
#FMC HPC HA
set_property PACKAGE_PIN G16 [get_ports "FMC_HPC_HA00_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA00_CC_N"]
set_property PACKAGE_PIN G17 [get_ports "FMC_HPC_HA00_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA00_CC_P"]
set_property PACKAGE_PIN D16 [get_ports "FMC_HPC_HA01_CC_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA01_CC_N"]
set_property PACKAGE_PIN E16 [get_ports "FMC_HPC_HA01_CC_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA01_CC_P"]
set_property PACKAGE_PIN H18 [get_ports "FMC_HPC_HA02_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA02_N"]
set_property PACKAGE_PIN H19 [get_ports "FMC_HPC_HA02_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA02_P"]
set_property PACKAGE_PIN G14 [get_ports "FMC_HPC_HA03_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA03_N"]
set_property PACKAGE_PIN G15 [get_ports "FMC_HPC_HA03_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA03_P"]
set_property PACKAGE_PIN F19 [get_ports "FMC_HPC_HA04_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA04_N"]
set_property PACKAGE_PIN G19 [get_ports "FMC_HPC_HA04_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC_HA04_P"]
Send Feedback

Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English