Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 122
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property PACKAGE_PIN AG14 [get_ports "DDR4_A15_CAS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A15_CAS_B"]
set_property PACKAGE_PIN AF14 [get_ports "DDR4_A16_RAS_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A16_RAS_B"]
set_property PACKAGE_PIN AF17 [get_ports "DDR4_BA0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA0"]
set_property PACKAGE_PIN AL15 [get_ports "DDR4_BA1"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BA1"]
set_property PACKAGE_PIN AG15 [get_ports "DDR4_BG0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_BG0"]
set_property PACKAGE_PIN AD21 [get_ports "DDR4_DM0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM0"]
set_property PACKAGE_PIN AE25 [get_ports "DDR4_DM1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM1"]
set_property PACKAGE_PIN AJ21 [get_ports "DDR4_DM2"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM2"]
set_property PACKAGE_PIN AM21 [get_ports "DDR4_DM3"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM3"]
set_property PACKAGE_PIN AH26 [get_ports "DDR4_DM4"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM4"]
set_property PACKAGE_PIN AN26 [get_ports "DDR4_DM5"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM5"]
set_property PACKAGE_PIN AJ29 [get_ports "DDR4_DM6"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM6"]
set_property PACKAGE_PIN AL32 [get_ports "DDR4_DM7"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DM7"]
set_property PACKAGE_PIN AH21 [get_ports "DDR4_DQS0_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS0_C"]
set_property PACKAGE_PIN AG21 [get_ports "DDR4_DQS0_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS0_T"]
set_property PACKAGE_PIN AJ25 [get_ports "DDR4_DQS1_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS1_C"]
set_property PACKAGE_PIN AH24 [get_ports "DDR4_DQS1_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS1_T"]
set_property PACKAGE_PIN AK20 [get_ports "DDR4_DQS2_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS2_C"]
set_property PACKAGE_PIN AJ20 [get_ports "DDR4_DQS2_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS2_T"]
set_property PACKAGE_PIN AP21 [get_ports "DDR4_DQS3_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS3_C"]
set_property PACKAGE_PIN AP20 [get_ports "DDR4_DQS3_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS3_T"]
set_property PACKAGE_PIN AL28 [get_ports "DDR4_DQS4_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS4_C"]
set_property PACKAGE_PIN AL27 [get_ports "DDR4_DQS4_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS4_T"]
set_property PACKAGE_PIN AP30 [get_ports "DDR4_DQS5_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS5_C"]
set_property PACKAGE_PIN AN29 [get_ports "DDR4_DQS5_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS5_T"]
set_property PACKAGE_PIN AJ33 [get_ports "DDR4_DQS6_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS6_C"]
set_property PACKAGE_PIN AH33 [get_ports "DDR4_DQS6_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS6_T"]
set_property PACKAGE_PIN AP34 [get_ports "DDR4_DQS7_C"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS7_C"]
set_property PACKAGE_PIN AN34 [get_ports "DDR4_DQS7_T"]
set_property IOSTANDARD DIFF_POD12_DCI [get_ports "DDR4_DQS7_T"]
set_property PACKAGE_PIN AE15 [get_ports "DDR4_CK_C"]
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English