Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 121
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ49"]
set_property PACKAGE_PIN AJ34 [get_ports "DDR4_DQ50"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ50"]
set_property PACKAGE_PIN AK31 [get_ports "DDR4_DQ51"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ51"]
set_property PACKAGE_PIN AJ31 [get_ports "DDR4_DQ52"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ52"]
set_property PACKAGE_PIN AJ30 [get_ports "DDR4_DQ53"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ53"]
set_property PACKAGE_PIN AH34 [get_ports "DDR4_DQ54"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ54"]
set_property PACKAGE_PIN AK32 [get_ports "DDR4_DQ55"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ55"]
set_property PACKAGE_PIN AN33 [get_ports "DDR4_DQ56"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ56"]
set_property PACKAGE_PIN AP33 [get_ports "DDR4_DQ57"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ57"]
set_property PACKAGE_PIN AM34 [get_ports "DDR4_DQ58"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ58"]
set_property PACKAGE_PIN AP31 [get_ports "DDR4_DQ59"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ59"]
set_property PACKAGE_PIN AM32 [get_ports "DDR4_DQ60"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ60"]
set_property PACKAGE_PIN AN31 [get_ports "DDR4_DQ61"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ61"]
set_property PACKAGE_PIN AL34 [get_ports "DDR4_DQ62"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ62"]
set_property PACKAGE_PIN AN32 [get_ports "DDR4_DQ63"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ63"]
set_property PACKAGE_PIN AE17 [get_ports "DDR4_A0"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A0"]
set_property PACKAGE_PIN AH17 [get_ports "DDR4_A1"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A1"]
set_property PACKAGE_PIN AE18 [get_ports "DDR4_A2"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A2"]
set_property PACKAGE_PIN AJ15 [get_ports "DDR4_A3"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A3"]
set_property PACKAGE_PIN AG16 [get_ports "DDR4_A4"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A4"]
set_property PACKAGE_PIN AL17 [get_ports "DDR4_A5"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A5"]
set_property PACKAGE_PIN AK18 [get_ports "DDR4_A6"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A6"]
set_property PACKAGE_PIN AG17 [get_ports "DDR4_A7"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A7"]
set_property PACKAGE_PIN AF18 [get_ports "DDR4_A8"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A8"]
set_property PACKAGE_PIN AH19 [get_ports "DDR4_A9"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A9"]
set_property PACKAGE_PIN AF15 [get_ports "DDR4_A10"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A10"]
set_property PACKAGE_PIN AD19 [get_ports "DDR4_A11"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A11"]
set_property PACKAGE_PIN AJ14 [get_ports "DDR4_A12"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A12"]
set_property PACKAGE_PIN AG19 [get_ports "DDR4_A13"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A13"]
set_property PACKAGE_PIN AD16 [get_ports "DDR4_A14_WE_B"]
set_property IOSTANDARD SSTL12_DCI [get_ports "DDR4_A14_WE_B"]
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English