Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 120
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property PACKAGE_PIN AK22 [get_ports "DDR4_DQ20"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ20"]
set_property PACKAGE_PIN AL24 [get_ports "DDR4_DQ21"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ21"]
set_property PACKAGE_PIN AL20 [get_ports "DDR4_DQ22"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ22"]
set_property PACKAGE_PIN AL23 [get_ports "DDR4_DQ23"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ23"]
set_property PACKAGE_PIN AM24 [get_ports "DDR4_DQ24"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ24"]
set_property PACKAGE_PIN AN23 [get_ports "DDR4_DQ25"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ25"]
set_property PACKAGE_PIN AN24 [get_ports "DDR4_DQ26"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ26"]
set_property PACKAGE_PIN AP23 [get_ports "DDR4_DQ27"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ27"]
set_property PACKAGE_PIN AP25 [get_ports "DDR4_DQ28"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ28"]
set_property PACKAGE_PIN AN22 [get_ports "DDR4_DQ29"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ29"]
set_property PACKAGE_PIN AP24 [get_ports "DDR4_DQ30"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ30"]
set_property PACKAGE_PIN AM22 [get_ports "DDR4_DQ31"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ31"]
set_property PACKAGE_PIN AH28 [get_ports "DDR4_DQ32"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ32"]
set_property PACKAGE_PIN AK26 [get_ports "DDR4_DQ33"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ33"]
set_property PACKAGE_PIN AK28 [get_ports "DDR4_DQ34"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ34"]
set_property PACKAGE_PIN AM27 [get_ports "DDR4_DQ35"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ35"]
set_property PACKAGE_PIN AJ28 [get_ports "DDR4_DQ36"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ36"]
set_property PACKAGE_PIN AH27 [get_ports "DDR4_DQ37"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ37"]
set_property PACKAGE_PIN AK27 [get_ports "DDR4_DQ38"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ38"]
set_property PACKAGE_PIN AM26 [get_ports "DDR4_DQ39"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ39"]
set_property PACKAGE_PIN AL30 [get_ports "DDR4_DQ40"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ40"]
set_property PACKAGE_PIN AP29 [get_ports "DDR4_DQ41"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ41"]
set_property PACKAGE_PIN AM30 [get_ports "DDR4_DQ42"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ42"]
set_property PACKAGE_PIN AN28 [get_ports "DDR4_DQ43"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ43"]
set_property PACKAGE_PIN AL29 [get_ports "DDR4_DQ44"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ44"]
set_property PACKAGE_PIN AP28 [get_ports "DDR4_DQ45"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ45"]
set_property PACKAGE_PIN AM29 [get_ports "DDR4_DQ46"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ46"]
set_property PACKAGE_PIN AN27 [get_ports "DDR4_DQ47"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ47"]
set_property PACKAGE_PIN AH31 [get_ports "DDR4_DQ48"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ48"]
set_property PACKAGE_PIN AH32 [get_ports "DDR4_DQ49"]
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English