Xilinx KCU105

KCU105 Board User Guide www.xilinx.com 119
UG917 (v1.4) September 25, 2015
Appendix D: Master Constraints File Listing
set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_N"]
set_property PACKAGE_PIN D23 [get_ports "USER_SMA_CLOCK_P"]
set_property IOSTANDARD LVDS [get_ports "USER_SMA_CLOCK_P"]
set_property PACKAGE_PIN L22 [get_ports "SI5328_INT_ALM_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SI5328_INT_ALM_LS"]
set_property PACKAGE_PIN K23 [get_ports "SI5328_RST_LS"]
set_property IOSTANDARD LVCMOS18 [get_ports "SI5328_RST_LS"]
set_property PACKAGE_PIN AH11 [get_ports "REC_CLOCK_C_N"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "REC_CLOCK_C_N"]
set_property PACKAGE_PIN AG11 [get_ports "REC_CLOCK_C_P"]
set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports "REC_CLOCK_C_P"]
set_property PACKAGE_PIN K20 [get_ports "FPGA_EMCCLK"]
set_property IOSTANDARD LVCMOS18 [get_ports "FPGA_EMCCLK"]
#SI570_CLOCK/SI5328 CLOCK SELECT
set_property PACKAGE_PIN F12 [get_ports "SI570_CLK_SEL_LS"]
set_property IOSTANDARD LVDS [get_ports "SI570_CLK_SEL_LS"]
#DDR4
set_property PACKAGE_PIN AE23 [get_ports "DDR4_DQ0"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ0"]
set_property PACKAGE_PIN AG20 [get_ports "DDR4_DQ1"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ1"]
set_property PACKAGE_PIN AF22 [get_ports "DDR4_DQ2"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ2"]
set_property PACKAGE_PIN AF20 [get_ports "DDR4_DQ3"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ3"]
set_property PACKAGE_PIN AE22 [get_ports "DDR4_DQ4"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ4"]
set_property PACKAGE_PIN AD20 [get_ports "DDR4_DQ5"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ5"]
set_property PACKAGE_PIN AG22 [get_ports "DDR4_DQ6"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ6"]
set_property PACKAGE_PIN AE20 [get_ports "DDR4_DQ7"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ7"]
set_property PACKAGE_PIN AJ24 [get_ports "DDR4_DQ8"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ8"]
set_property PACKAGE_PIN AG24 [get_ports "DDR4_DQ9"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ9"]
set_property PACKAGE_PIN AJ23 [get_ports "DDR4_DQ10"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ10"]
set_property PACKAGE_PIN AF23 [get_ports "DDR4_DQ11"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ11"]
set_property PACKAGE_PIN AH23 [get_ports "DDR4_DQ12"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ12"]
set_property PACKAGE_PIN AF24 [get_ports "DDR4_DQ13"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ13"]
set_property PACKAGE_PIN AH22 [get_ports "DDR4_DQ14"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ14"]
set_property PACKAGE_PIN AG25 [get_ports "DDR4_DQ15"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ15"]
set_property PACKAGE_PIN AL22 [get_ports "DDR4_DQ16"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ16"]
set_property PACKAGE_PIN AL25 [get_ports "DDR4_DQ17"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ17"]
set_property PACKAGE_PIN AM20 [get_ports "DDR4_DQ18"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ18"]
set_property PACKAGE_PIN AK23 [get_ports "DDR4_DQ19"]
set_property IOSTANDARD POD12_DCI [get_ports "DDR4_DQ19"]
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