KCU105 Board User Guide www.xilinx.com 48
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
On power-up, or on reset, the PHY is configured to operate in SGMII mode with PHY
address 0b00111 using the settings shown in Table 1-15. These settings can be over
written via software commands passed over the MDIO interface.
Table 1-15: Board Connections for PHY Configuration Pins
Pin Bit[2] Bit[1] Bit[0]
Default
Values for
Bit[2:0]
Setting Description
CFG0 PHYADR[2] PHYADR[1] PHYADR[0] 111 PHYAddr 00111. Do not
advertise the PAUSE bit.
CFG1 ENA_PAUSE PHYADR[4] PHYADR[3] 000
CFG2 ANEG[3] ANEG[2] ANEG[1] 111 Auto-Neg en, advertise all
caps; prefer slave. Auto
crossover enabled.
125 MHz CLK option
disabled.
CFG3 ANEG[0] ENA_XC DIS_125 111
CFG4 HWCFG_MD[2] HWCFG_MD[1] HWCFG_MD[0] 100 SGMII to Cu mode.
Fiber/copper auto-detect
disabled. Sleep mode
disabled.
CFG5 DIS_FC DIS_SLEEP HWCFG_MD[3] 110
CFG6 SEL_BDT INT_POL 75/50
Ω 010
MDC/MDIO selected.
Active Low interrupt. 50 Ω
SERDES option.
Table 1-16: FPGA U1 to Ethernet PHY U58 Connections
FPGA (U1)
Pin
Net Name I/O Standard
M88E1111 PHY U58
Pin Name
H26 PHY_MDIO LVCMOS18 M1 MDIO_SDA
L25 PHY_MDC LVCMOS18 L3 MDC_SCL
K25 PHY_INT LVCMOS18 L1 INT_B
J23 PHY_RESET LVCMOS18 K3 RESET_B
Notes:
Ethernet PHY_ U58 signals are level-shifted to 1.8V for interface to FPGA U1 bank 65.
X-Ref Target - Figure 1-19
Figure 1-19: Ethernet PHY J45 Configuration Jumper J45
-
+'5B;
3+<B/('B/,1.
8*BB
3+<B&21),*
*1'
-SLQV6*0,,WR&XZLWKRXW&ORFN
-SLQV6*0,,WR&XZLWK&ORFN'()$8/7
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