Xilinx VC707 User Manual

106 www.xilinx.com VC707 Evaluation Board
UG885 (v1.4) May 12, 2014
Appendix C: Master Constraints File Listing
set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
set_property PACKAGE_PIN E24 [get_ports DDR3_D40]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
set_property PACKAGE_PIN D23 [get_ports DDR3_D41]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
set_property PACKAGE_PIN D26 [get_ports DDR3_D42]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
set_property PACKAGE_PIN C25 [get_ports DDR3_D43]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
set_property PACKAGE_PIN E23 [get_ports DDR3_D44]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
set_property PACKAGE_PIN D22 [get_ports DDR3_D45]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
set_property PACKAGE_PIN F22 [get_ports DDR3_D46]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
set_property PACKAGE_PIN E22 [get_ports DDR3_D47]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
set_property PACKAGE_PIN A30 [get_ports DDR3_D48]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
set_property PACKAGE_PIN D27 [get_ports DDR3_D49]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
set_property PACKAGE_PIN A29 [get_ports DDR3_D50]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
set_property PACKAGE_PIN C28 [get_ports DDR3_D51]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
set_property PACKAGE_PIN D28 [get_ports DDR3_D52]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
set_property PACKAGE_PIN B31 [get_ports DDR3_D53]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
set_property PACKAGE_PIN A31 [get_ports DDR3_D54]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
set_property PACKAGE_PIN A32 [get_ports DDR3_D55]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
set_property PACKAGE_PIN E30 [get_ports DDR3_D56]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
set_property PACKAGE_PIN F29 [get_ports DDR3_D57]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
set_property PACKAGE_PIN F30 [get_ports DDR3_D58]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
set_property PACKAGE_PIN F27 [get_ports DDR3_D59]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
set_property PACKAGE_PIN C30 [get_ports DDR3_D60]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
set_property PACKAGE_PIN E29 [get_ports DDR3_D61]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
set_property PACKAGE_PIN F26 [get_ports DDR3_D62]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
set_property PACKAGE_PIN D30 [get_ports DDR3_D63]
set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
set_property PACKAGE_PIN N16 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN M16 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
set_property PACKAGE_PIN K12 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN J12 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN H16 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS2_P]
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Xilinx VC707 Specifications

General

Brand	Xilinx
Model	VC707
Category	Motherboard
Language	English