Xilinx Virtex-6 FPGA Getting Started Guide

Virtex-6 FPGA Connectivity Kit Getting Started www.xilinx.com 67
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
b. Connect J6 to J8 (see Figure 66).
c. Connect J3 to J9 (see Figure 67).
X-Ref Target - Figure 66
Figure 66: Configuring the SMA Transceiver Channel with External Loopback - II
X-Ref Target - Figure 67
Figure 67: Configuring the SMA Transceiver Channel with External Loopback - III
UG664_43_021810
UG664_44_021810

Xilinx Virtex-6 FPGA Specifications

General

Brand	Xilinx
Model	Virtex-6 FPGA
Category	Transceiver
Language	English