Xilinx Virtex-6 FPGA

68 www.xilinx.com Virtex-6 FPGA Connectivity Kit Getting Started
UG664 (v1.4) July 6, 2011
Getting Started with the Virtex-6 FPGA IBERT Reference Design
d. Connect J5 to J7 (see Figure 68).
e. Connect J11 to J12 with a SATA loopback cable included in the Virtex-6 FPGA
Connectivity Kit (see Figure 69).
X-Ref Target - Figure 68
Figure 68: Configuring the SMA Transceiver Channel with External Loopback - IV
X-Ref Target - Figure 69
Figure 69: Configuring the SMA Transceiver Channels and SATA Channels with
External Loopback - V
UG664_45_011610
UG664_46_011610