Xilinx Virtex-7 FPGA VC7222 IBERT - Extracting the Project Files

VC7222 IBERT Getting Started Guide www.xilinx.com 7
UG971 (v5.0) June 12, 2014
Extracting the Project Files
d. Screw down a 50Ω SMA terminator onto each of the six unused Si5368 clock
output SMA connectors: J7, J8, J12, J15, J16, and J17.
Extracting the Project Files
The Vivado project files required to run the IBERT demonstration are located in
rdf0297-vc7222-ibert-2014-2.zip on the SD card provided with the VC7222
board. These files are also available online at the Virtex-7 FPGA VC7222 Characterization
Kit documentation website.
The ZIP file contains these files:
•BIT files
vc7222_ibert_q113_325.bit
vc7222_ibert_q114_325.bit
vc7222_ibert_q115_325.bit
vc7222_ibert_q213_325.bit
vc7222_ibert_q214_325.bit
vc7222_ibert_q215_325.bit
vc7222_ibert_q300_225.bit
vc7222_uarttest.bit
•Probe files
vc7222_ibert_q113_debug_nets.ltx
vc7222_ibert_q114_debug_nets.ltx
vc7222_ibert_q115_debug_nets.ltx
vc7222_ibert_q213_debug_nets.ltx
vc7222_ibert_q214_debug_nets.ltx
vc7222_ibert_q215_debug_nets.ltx
vc7222_ibert_q300_debug_nets.ltx
•Tcl scripts
add_scm2.tcl
setup_scm2_325_00_GTH.tcl
setup_scm2_225_00_GTZ.tcl
The Tcl scripts are used to help merge the IBERT and SuperClock-2 source code (described
in Chapter 2, Creating the GTH IBERT Core and in Chapter 3, Creating the GTZ IBERT
Core) and to set up the SuperClock-2 module (described in Starting the SuperClock-2
Module, page 18 in the GTH section and Starting the SuperClock-2 Module, page 31 in the
GTZ section).
To copy the files from the SD memory card:
1. Connect the SD card to the host computer.
2. Locate the file rdf0297-vc7222-ibert-2014-2.zip on the SD memory card.
3. Unzip the files to a working directory on the host computer.
Send Feedback