38 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 1: VC7222 IBERT Getting Started Guide
Viewing the GTZ Transceiver Operation
After completing step 6, page 37 in Starting the SuperClock-2 Module, page 31, the IBERT
demonstration is configured and running. The link status and test settings are displayed
on the Serial IO Links tab in the Links Window shown in Figure 1-33.
Note the line rate and RX bit error count:
• The line rate for all GTZ transceivers is 28.05 Gb/s (see the Status Column in
Figure 1-33).
• Verify that there are no bit errors.
Note:
External or internal CTLE tuning might be required for successful GTZ operation. If the Link
Status shows No Link for one or more transceivers, click the respective lane CTLE Tune button
(
Figure 1-33).
In Case of RX Bit Errors
If there are initial bit errors after linking, or as a result of changing the TX or RX pattern,
click the respective BERT Reset button to zero the count.
Additional information on the Vivado Design Suite and IBERT core can be found in Vivado
Design Suite User Guide: Programming and Debugging (UG908) [Ref 3] and in LogiCORE IP
Integrated Bit Error Ratio Tester (IBERT) for 7 Series GTX Transceivers Product Guide for Vivado
Design Suite (PG132) [Ref 4].
X-Ref Target - Figure 1-33
Figure 1-33: Serial I/O Analyzer Links
To Next Page
Loading...
Need help?
General
