Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

VC7222 IBERT Getting Started Guide www.xilinx.com 37
UG971 (v5.0) June 12, 2014
Running the GTZ IBERT Demonstration
6. If links are created manually, the Create Links window is displayed. The options in this
window are used to link any TX GT to any RX GT. To create links, select the TX GT and
RX GT from the two lists, then click the Add Link button. For this project, connect
the following links (Figure 1-32):
• Lane0/TX to Lane0/RX
• Lane1/TX to Lane1/RX
• Lane2/TX to Lane2/RX
• Lane3/TX to Lane3/RX
• Lane4/TX to Lane4/RX
• Lane5/TX to Lane5/RX
• Lane6/TX to Lane6/RX
• Lane7/TX to Lane7/RX
X-Ref Target - Figure 1-32
Figure 1-32: Create Links Window
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English