Xilinx Virtex-7 FPGA VC7222 IBERT User Manual

VC7222 IBERT Getting Started Guide www.xilinx.com 25
UG971 (v5.0) June 12, 2014
Running the GTZ IBERT Demonstration
Closing the IBERT Demonstration
To stop the IBERT demonstration:
1. Close the Vivado Design Suite application by selecting File > Exit.
2. Place the main power switch SW1 in the off position.
Running the GTZ IBERT Demonstration
The GTZ IBERT demonstration example provided here operates all 8 lanes of the GTZ
transceiver at the same time.
Connecting the GTZ Transceiver and Reference Clocks
Figure 1-20 shows the locations for the two GTZ transceiver Quads (GTZ Quads Q300A
and Q300B) on the Rev. B VC7222 board.
X-Ref Target - Figure 1-20
Figure 1-20: GTZ Quad Location
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Xilinx Virtex-7 FPGA VC7222 IBERT Specifications

General

Brand	Xilinx
Model	Virtex-7 FPGA VC7222 IBERT
Category	Motherboard
Language	English