Xilinx Virtex-7 VC7203 User Manual

VC7203 GTX Transceiver Characterization Board www.xilinx.com 67
UG957 (v1.3) October 17, 2014
VC7203 Board XDC Listing
set_property PACKAGE_PIN J17 [get_ports CM_CTRL_23]
set_property IOSTANDARD LVCMOS18 [get_ports CM_CTRL_23]
set_property PACKAGE_PIN E12 [get_ports CM_LVDS1_P]
set_property IOSTANDARD LVDS [get_ports CM_LVDS1_P]
set_property PACKAGE_PIN D12 [get_ports CM_LVDS1_N]
set_property IOSTANDARD LVDS [get_ports CM_LVDS1_N]
set_property PACKAGE_PIN L12 [get_ports CM_LVDS2_P]
set_property IOSTANDARD LVDS [get_ports CM_LVDS2_P]
set_property PACKAGE_PIN L11 [get_ports CM_LVDS2_N]
set_property IOSTANDARD LVDS [get_ports CM_LVDS2_N]
set_property PACKAGE_PIN BA12 [get_ports CM_LVDS3_P]
set_property IOSTANDARD LVDS [get_ports CM_LVDS3_P]
set_property PACKAGE_PIN BB12 [get_ports CM_LVDS3_N]
set_property IOSTANDARD LVDS [get_ports CM_LVDS3_N]
set_property PACKAGE_PIN K19 [get_ports CM_GCLK_P]
set_property IOSTANDARD LVCMOS18 [get_ports CM_GCLK_P]
set_property PACKAGE_PIN J18 [get_ports CM_GCLK_N]
set_property IOSTANDARD LVCMOS18 [get_ports CM_GCLK_N]
#SWITCHES
set_property PACKAGE_PIN E42 [get_ports USER_SW1]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW1]
set_property PACKAGE_PIN C40 [get_ports USER_SW2]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW2]
set_property PACKAGE_PIN C41 [get_ports USER_SW3]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW3]
set_property PACKAGE_PIN H40 [get_ports USER_SW4]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW4]
set_property PACKAGE_PIN H41 [get_ports USER_SW5]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW5]
set_property PACKAGE_PIN H39 [get_ports USER_SW6]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW6]
set_property PACKAGE_PIN G39 [get_ports USER_SW7]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW7]
set_property PACKAGE_PIN G41 [get_ports USER_SW8]
set_property IOSTANDARD LVCMOS18 [get_ports USER_SW8]
#BUTTONS
set_property PACKAGE_PIN P41 [get_ports USER_PB1]
set_property IOSTANDARD LVCMOS18 [get_ports USER_PB1]
set_property PACKAGE_PIN N41 [get_ports USER_PB2]
set_property IOSTANDARD LVCMOS18 [get_ports USER_PB2]
#SMAs
set_property PACKAGE_PIN H19 [get_ports CLK_DIFF_1_P]
set_property IOSTANDARD LVCMOS18 [get_ports CLK_DIFF_1_P]
set_property PACKAGE_PIN G18 [get_ports CLK_DIFF_1_N]
set_property IOSTANDARD LVCMOS18 [get_ports CLK_DIFF_1_N]
set_property PACKAGE_PIN K39 [get_ports CLK_DIFF_2_P]
set_property IOSTANDARD LVCMOS18 [get_ports CLK_DIFF_2_P]
set_property PACKAGE_PIN K40 [get_ports CLK_DIFF_2_N]
set_property IOSTANDARD LVCMOS18 [get_ports CLK_DIFF_2_N]
#SYSTEM CLOCKS
set_property PACKAGE_PIN E19 [get_ports LVDS_OSC_P]
set_property IOSTANDARD LVDS [get_ports LVDS_OSC_P]
set_property PACKAGE_PIN E18 [get_ports LVDS_OSC_N]
set_property IOSTANDARD LVDS [get_ports LVDS_OSC_N]
#LEDs
set_property PACKAGE_PIN M37 [get_ports APP_LED1]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED1]
set_property PACKAGE_PIN M38 [get_ports APP_LED2]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED2]
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Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial