Xilinx Virtex-7 VC7203 User Manual

68 www.xilinx.com VC7203 GTX Transceiver Characterization Board
UG957 (v1.3) October 17, 2014
Appendix C: Master Constraints File Listing
set_property PACKAGE_PIN R42 [get_ports APP_LED3]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED3]
set_property PACKAGE_PIN P42 [get_ports APP_LED4]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED4]
set_property PACKAGE_PIN N38 [get_ports APP_LED5]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED5]
set_property PACKAGE_PIN M39 [get_ports APP_LED6]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED6]
set_property PACKAGE_PIN R40 [get_ports APP_LED7]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED7]
set_property PACKAGE_PIN P40 [get_ports APP_LED8]
set_property IOSTANDARD LVCMOS18 [get_ports APP_LED8]
#IIC
set_property PACKAGE_PIN M41 [get_ports DUT_I2C_SCL]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_I2C_SCL]
set_property PACKAGE_PIN L41 [get_ports DUT_I2C_SDA]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_I2C_SDA]
#PMBUS
set_property PACKAGE_PIN E40 [get_ports DUT_PMB_ALERT]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_PMB_ALERT]
set_property PACKAGE_PIN D40 [get_ports DUT_PMB_CTRL]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_PMB_CTRL]
set_property PACKAGE_PIN A40 [get_ports DUT_PMB_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_PMB_CLK]
set_property PACKAGE_PIN A41 [get_ports DUT_PMB_DATA]
set_property IOSTANDARD LVCMOS18 [get_ports DUT_PMB_DATA]
#USB_GPIOs
set_property PACKAGE_PIN B28 [get_ports USB_GPIO_0]
set_property IOSTANDARD LVCMOS18 [get_ports USB_GPIO_0]
set_property PACKAGE_PIN B29 [get_ports USB_GPIO_1]
set_property IOSTANDARD LVCMOS18 [get_ports USB_GPIO_1]
set_property PACKAGE_PIN A31 [get_ports USB_GPIO_2]
set_property IOSTANDARD LVCMOS18 [get_ports USB_GPIO_2]
set_property PACKAGE_PIN A32 [get_ports USB_GPIO_3]
set_property IOSTANDARD LVCMOS18 [get_ports USB_GPIO_3]
#UART
set_property PACKAGE_PIN A29 [get_ports USB_TXD_0]
set_property IOSTANDARD LVCMOS18 [get_ports USB_TXD_0]
set_property PACKAGE_PIN A30 [get_ports USB_RXD_I]
set_property IOSTANDARD LVCMOS18 [get_ports USB_RXD_I]
set_property PACKAGE_PIN C31 [get_ports USB_RTS_0_B]
set_property IOSTANDARD LVCMOS18 [get_ports USB_RTS_0_B]
set_property PACKAGE_PIN B31 [get_ports USB_CTS_I_B]
set_property IOSTANDARD LVCMOS18 [get_ports USB_CTS_I_B]
#SPI
set_property PACKAGE_PIN A24 [get_ports MGT_MOD_SPI_SCK]
set_property IOSTANDARD LVCMOS18 [get_ports MGT_MOD_SPI_SCK]
set_property PACKAGE_PIN A25 [get_ports MGT_MOD_SPI_D]
set_property IOSTANDARD LVCMOS18 [get_ports MGT_MOD_SPI_D]
set_property PACKAGE_PIN B22 [get_ports MGT_MOD_SPI_Q]
set_property IOSTANDARD LVCMOS18 [get_ports MGT_MOD_SPI_Q]
set_property PACKAGE_PIN A22 [get_ports GTX_MOD_SPI_CS]
set_property IOSTANDARD LVCMOS18 [get_ports GTX_MOD_SPI_CS]
#MGTs
set_property PACKAGE_PIN AW10 [get_ports 111_REFCLK0_P]
set_property PACKAGE_PIN AW9 [get_ports 111_REFCLK0_N]
set_property PACKAGE_PIN BA10 [get_ports 111_REFCLK1_P]
set_property PACKAGE_PIN BA9 [get_ports 111_REFCLK1_N]
set_property PACKAGE_PIN AW2 [get_ports 111_TX3_P]
Send Feedback

Xilinx Virtex-7 VC7203 Specifications

General

FPGA Family	Virtex-7
Transceiver	GTH
GTH Transceivers	16
Maximum Data Rate	13.1 Gbps
Transceivers	16
Maximum Transceiver Speed	13.1 Gbps
Maximum User I/O	600
Process Technology	28nm
Block RAM	38 Mb
Power Supply Voltage	0.9V
Operating Temperature Range	Industrial