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ZiLOG System 8000 Hardware Reference Manual

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HRM
3IGNAL
NAME\
MNEMONIC
MMAO\
p~rRBAD\
MCLK
BCLK
RESET\
2ilog
HRM
NUMBER
FUNCTION
OF
LINES
Multimicro
Acknowledge
Out:
This
signal
works
with
signal
MMAI\
to
form
the
resource-
request
daisy
chain.
Power
Bad:
The
processor
power
supply
generates
this
as
an
early
warning
to
the
system
that
the
DC
power
will
soon
disappear.
Master
Clock:
This
signal
is
the
system
clock
and
is
the
foundation
for
all
timing
in
the
system.
The
frequency
of
the
MCLK
signal
is
four
times
(4X)
that
of
the
bus
clock
(BCLK).
Bus
Clock:
The
system
derives
this
clock
from
the
master
clock
(MCLK).
The
BCLK
is
one
fourth
the
frequency
of
the
master
clock
and
synchronizes
the
operation
of
the
elements
in
the
system
that
require
synchronization.
All
bus
transfers
are
synchronized
to
this
clock.
The
system
CPU
board
is
the
generator
of
this
clock
and
'MCLK
above.
:Reset:
This
is
the
master
reset
signal
for
the
entire
system.
This
signal
is
generated
by
the
front
panel
master
reset
switch
or
upon
power-up
by
the
power-up
reset
circuit.
When
it
is
forced
low,
it
initializes
the
E~n
tire
system.
4-7
2ilog
4-7

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ZiLOG System 8000 Specifications

General IconGeneral
BrandZiLOG
ModelSystem 8000
CategoryDesktop
LanguageEnglish

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