ZiLOG System 8000 Hardware Reference Manual

HRM
4.5. Bus Modules
Zilog
HRM
The bus modules are the major blocks that communicate
directly with the CPU over the bus. The one exception is
the ECC Memory Array module whose communications path to the
bus is through the Memory Subsystem Controller. The follow-
ing paragraphs deal more closely with the individual
modules.
4.5.1. CPU Module: The CPU module is the bus controller,
sometimes called the host, which initiates and controls
transactions on the bus. Also as shown in Figure 4-2, the
CPU connects directly to and controls the I/O bus. All
transactions with the outside world pass through either the
parallel port or one of the eight serial I/O ports. The I/O
lines from the CPU module pass through mating connectors P2
and J21, located on the CPU module and backplane, respec-
tively. Table 4-4 lists the lines on the CPU I/O bus and
their definitions.
Table 4-4 CPU I/O Bus, Signal Definitions
.SIGNAL NAME DEFINITION
TXD7 to TXDO Transmit Data, 8 bits
RXD7 to RXDO Receive Data, 8 bits
CTS7 to eTSO Clear to Send
DTR7 to DTSO Data Terminal Ready
RTS7 to RTSO Request to Send
DSR7 to DSRO Data Set Ready
TXRTN7 to TXRTNO Transmit Return
DATA7 to DATAO PIO Data
DATA STROBE Data Products Data Strobe
DATA STROBE\ Centronics Data Strobe, Active low
4-9
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4-9

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English