ZiLOG System 8000 Hardware Reference Manual

HRM
Zilog HRM
The status lines, ST<4:0>, and the data width lines, B/W\
and W/LW\, form specific codes that cause a number of
discrete operations to occur. Tables 4-2 and 4-3 list the
various codes on the status and data width lines respec-
tively, and the operations that the codes initiate.
Table 4-1 Bus Lines
SIGNAL
NAME\
MNEMONIC
AD<31:0>
ST<4:0>
R/W\
N/S\
4-3
NUMBER
OF
LINES
32
5
FUNCTION
Multiplexed Address/Data lines:
These lines are driven by the
bus master. The address strobe
(AS\) and data strobe (DS\)
determine when the information
on these lines is valid.
Memory Error:
During a memory access, if the
memory controller detects an
uncorrectable error, the
controller sends the ME\ signal
to the bus master.
Status Lines:
These active-high lines indicate
the type of transaction currently
occurring on the bus. (See Table
4-2 for the various codings and
their associated transactions.)
Read-Write:
This is a dual-purpose line. When
this line is high, it indicates
that the current operation is a
read operation; when the line is
low, the operation is a write
operation.
Normal-System:
Indicates the mode of operation
of the master that is currently
controlling the bus.
Zilog
4-3

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English