ZiLOG System 8000

HRM
Zilog
HRM
1 M
ECC MEMORY
1M
ECC MEMORY
r 0;;:101; - - - - - - - - - - "I
: EGG ~~MORY ] EGG ~~MORY :
I I
L~ £~
I I
I I
I
~'j7' ~ I "",-.-7
I ~ MEMORY BUS CONNECTOR P2/J2
I _ _ _ _ _ __ _ _ _ _ £';::... BACKPLANE SLOTS: J28-J30
OR J26·J30
MEMORY
SUBSYSTEM
CONTROLLER
"7 P1/J1
Z·BUS BACKPLANE INTERCONNECT (ZBI)
?
00159
Figure 4-10 Memory SUbsystem Controller,
Functional Relationships
BIT 38
I
BIT 31
I
BIT 23
I
BIT 15
I
BIT 07
I
BIT 00
I
CHECK BITS BYTE 0
BYTE 1
BYTE 2
BYTE 3
CHECK BIT!~
BYTE 4
BYT.E 5
BYTE 6
BYTE 7
CHECK
BlTn
BYTE 8
BYTE 9
BYTE 10
BYTE 11
(ADDITIONAL BYTES)
CHECK BITS
BYTE N·3 BYTE N·2
BYTE
N·1
BYTE N
I
BIT 38
I
BIT 31
I
BIT 23
I
BIT 15
I
BIT 07
I
BIT 00
o0 170
Figure 4-11
Memory Organization
4-59
Zilog
4-59