ZiLOG System 8000 Hardware Reference Manual

HRM
Zilog
HRM
Once IP is turned on or the interrupt acknowledged, the host
reads SR and then issues CR:RI to reset IP and IUS regard-
less of whether the interrupts were enabled. Once IP is
reset, the controller may interrupt again. The interrupt
enable flag in the controller is reset by CR:DI, which may
be issued with CR:RI if desired.
Ending status and interrupting drive number are made avail-
able in the high order byte of the interrupt vector returned
by the controller during an interrupt acknowledge transac-
tion. The drive number is also available in SR:DRV until
CR:RI is issued.
Packet
15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
--------------------------------------------------
: head bias & volume select
: 0 10 : ending status
byte by sector count
lRZIRTlEC:
:0-:0 ... :
CMD
:SMlXM:BZIROIFTISElOClRY\
SEL
lNRlNE:NOl
:SLlSE\
unit
cylinder
head
dma address 23-16
dma address 15-0
sector
reserved
o
SKE
lFSINWl
00
CM
02 ST
04 SB
06 DS
08
CT
OA AH
OC
AL
OE UN
10
CY
12
HD
14
VS
16
SC
18
OF
1A-1E
15 14 13 12
11 10 9 8 7 6 5 4 3
')
c_
o
4-32
Zilog
4-32

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English