ZiLOG System 8000 Hardware Reference Manual

HRM
Zilog
Table 4-18 ZBI Tape Controller Interface Registers
HRM
ADDRESS
40H
42H
44H
46H
48H
4AH
4-47
REGISTER
Interrupt Vector
Command
Low DMA Start Address
High DMA Start Address
DMA Length
St'3tus
Zilog
DESCRIPTION
The low-order byte con-
tains the interrupt vec-
tor that host CPU writes
to the controller.
The high-order byte con-
tains status information
that the controller sends
to the host.
The host sends commands
to this register. The
controller accepts only
valid commands.
The host sends the low
word of the DMA starting
address in this register.
Bit 0 of this byte must
be a 0 so that the
address starts on a word
boundary.
This register contains
the high-order byte (bits
16 to 23) of the DMA
start address.
This register contains
the length of the DMA
transfer. This value must
be less than 32 kilobytes
( 1 k= 1 024) .
The controller stores in-
formation about the tape
drive and controller in
this register. The host
reads this information.
Another table defines the
bits.
4-47

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English