ZiLOG System 8000 Hardware Reference Manual

HRM
SIGNAL
NAME\
MNEMONIC
BUSREQ\
CAI\
CAO\
CPUREQ\
CAVAIL
INT1\
INT2\
Zilog HRM
NUMBER FUNCTION
OF
LINES
Bus
Request:
A module uses the BUSREQ\ signal
to gain access to the bus. This
signal is part of the priority
scheme that is set up by the
connection of signals BAI\ and
BAO\.
CPU Acknowledge In: .
Not
currently implemented--the
CAI, CAO, CPUREQ, CAVAIL signals
are designed to allow multiple
CPUs to share a single bus. They
may be used on a future S8000 product
and should be considered reserved.
CPU Acknowledge Out:
Not currently implemented--
Ireserved
CPU Request:
Not currently implemented--
reserved
CPU Available:
Not currently implemented--
reserved
Level-1 Interrupt:
This interrupt line has the
highest priority in the system.
This line when driven by a
slave generates a non-maskable
tnterrupt (NMI).
Level-2 Interrupt:
This interrupt line has the
second to the highest priority
in the system. This line, when
driven by a slave, generates a
vectored interrupt.
Zilog
4-5

ZiLOG System 8000 Specifications

General

Brand	ZiLOG
Model	System 8000
Category	Desktop
Language	English