ZOLL PD 2000 - Page 66

FUNCTIONAL DESCRIPTION
ARCHITECTURAL OVERVIEW
SA. CPU
The CPU and EPU use separate address and data busses. Communication
between CPU and EPU is on a single line network which is also shared
with external modules through the Option Module Port. An I/O
controller gate array shares bus with the CPU and provides device
control latches and data input latches as well as timing and other
functions under read/write control of the CPU. The CPU also has bus
control of A/D and D/A for analog control and measurement and bus
control of latches for control of other devices such as the strip chart
recorder.
A CRT display controller gate array has its own RAM/ROM bus and
functions as a dedicated controller. The EPU controls the display
controller by writing to a CRT control latch and by writing to a bi-
directional bus chip that allows the EPU and CRT controller buses to be
common. The EPU also has bus control of parallel to serial and serial to
parallel data conversion for ECG data and control.
The CPU is the central control for the PD™ 1400series instruments. It
receives information from the front panel switches and from signals
internal to the instrument. After making decisions based upon the
information received, it controls the operation of functional blocks such
as the pacer output, defibrillator output, the strip chart recorder, the real
time clock, and the non-volatile memory.
The basic hardware functional blocks associated with the CPU are as
follows:
1. Front panel I/O control
2. Microprocessor (CPU, ROM, RAM, NVRAM, memory
control)
3. Real time clock
4, Input and output latches
5. Analog-to-Digital conversion
6. Digital-to-Analog conversion
7. Serial communication
All the user inputs from the front panel are received by the CPU. The
CPU then distributes the appropriate signals as required.
The CPU passes control requirements for ECG to the EPU by way of the
serial communication link.
IV-7