ZOLL PD 2000 - Page 67

SERVICE MANUAL
Operation of the pacer function is performed by having all the user setup
controls received by the CPU. Signals such as pace current amplitude and
pace pulse rate are converted from analog signals to digital data for
microprocessor operation and manipulation.
The pacer operates as an output device controlled by the CPU. Pace
current amplitude is set through a D/A converter (VCTL) and pace pulse
width and rate is set by the gate array signal XPWRENB. See section 4b.
The defibrillator charging and discharging is controlled by the CPU. The
CPU receives all the user inputs and performs all the required logic for
safe operation of the defibrillator except for the independent safety
checks performed by the EPU. Diagnostic functions concerning the
proper high voltage capacitor charging and operation of the defibrillator
are provided by the analog signal VCAP representing the high voltage
capacitor voltage.
The defib energy delivered is calculated by the CPU from a signal
derived from the wave shaping coil.
CPU HARDWARE
The CPU circuits center on a 8031 microcomputer (U27).
The CPU performs several checks on internal circuits to be sure that they
are running properly including all memory locations, voltage reference
and the real time clock.
All digital input signals to the CPU go to individual latches or to the on
board gate array (U21). These signals are read into the RAM memory.
Digital output control signals are provided on discrete latches or on the
gate array (U21).
The real time clock (U58) retains date and time. When the instrument is
turned off, the real time clock operates at reduced voltage and draws
insignificant current from the battery. When the battery pack is removed,
a large capacitor provides operating power to the real time clock for eight
or more hours.
The CPU controls and monitors all the controls and switches on the
instrument and the paddles or Multi-Function Cable and accessory
cables. (Option module) The front panel switches are read into a matrix
array of rows and columns (SWCOLO-3 and SWROWO-5) that the CPU
can read through the gate array to determine which switches have been
selected. The CPU also monitors the presence and identification of option
‘ modules and accessory cables.