ZOLL PD 2000 - Page 68

FUNCTIONAL DESCRIPTION
The gate array has several independent functions collected into a single
LSIC. Several of the internal functions have been described as they
pertain to specific functional operations of the CPU. Additional functions
in the gate array are clock divider circuits, pacer timing and control
signals and an independent watchdog timer and reset circuit.
The watch dog timer provides functional safety in the event of a failure in
the microprocessor program execution. If the microprocessor fails to
update the watchdog timer every 4.5 msec the timer will reset the CPU.
The analog section of the CPU circuit consists of analog-to-digital (A/D)
conversion and digital-to-analog (D/A) conversion. The (A/D) section
has an 8 bit successive approximation converter (U16). Two multiplexers
(U6 and U8) provide 16 analog inputs:
Channel 0 BEEP /PWR_STROBE beeper
Channel 1 PADMON paddles switches status
Channel 2 RPOT Pacer rate-setting potentiometer voltag:
Channel 3 V_PADPOTI paddle buttons
Channel 4 VCAP high voltage capacitor
Channel 5 V_PADPOT2 paddle type
Channel 6 IPOT Pacer output current setting potentiom
voltage
Channel 7 SWBATT battery voltage
‘| Channel 8 ECGOUT,VCTL_LOOP test
Channel 9 V_X, V_Y_LOOP test
Channel 10 TEMP_SNS temperature
Channel 11 CHARGE defib charge button
Channel 12 CATH_LOOP test
Channel 13 IPEAK defib discharge current
Channel 14 PACE ID test
Channel 15 25V REF voltage reference
The reference voltages required for both A/D and D/A are provided by
5V_REF2, derived from 25V_REF (U20). ©
IV-9