ZOLL PD 2000 - Page 71

SERVICE MANUAL
The gate array has five control registers used to drive the CRT deflection
circuits, to control the beam intensity, and to set up operating modes
such as clock rate and filter selection (trace vs character).
The five registers are defined as follows:
» X latch - 8 bit data to drive a DAC for horizontal beam
deflection.
e Y latch - 8 bit data to drive a DAC for vertical beam deflection.
* Intensity Latch - 8 bits (U52-1 to 6, 9,10) of individually elected
lines to set beam intensity and clock rate.
* Blanking shift Register - An 8 bit word is shifted out serially
(U52-7, BENBO) for each new X and Y data word. This is used
only during character display.
» Attribute Latch - 4 bits individually selected to control
operating modes such as end of message (EOMC), blink
enable, filter control (EXTR3).
The gate array can read the ROM (U55) and is capable of reading and
writing RAM (U56). The RAM is used to store 1000 bytes of ECG data
with an R-wave marker, store a sequence of starting ROM addresses for
characters, store ROM addresses for programmed wait and move
instructions, and provide a stack for subroutine operations.
To display a trace on the CRT, the gate array will retrieve a single Y data
point from RAM every 8 sec and latch it into the Y DAC register. Every
32 tisec the X DAC is incremented by one count having started at a count
of 00Hex (left side of CRT display). Each Y data point also has an
intensity and blanking byte to control the beam intensity. When an R-
wave is detected, the sixth intensity bit (slew) i is set high to further
intensify the beam. For normal trace intensity the fifth intensity bit (Intfy)
is set high. The blanking byte is not used in the trace mode.
During the character display mode, the gate array retrieves the character
generation commands from the ROM every 4 psec. Each command will
provide an X and Y incremental movement and a blanking byte (BENBO)
to control intensity. The blanking byte is modulated during each step
command to provide a constant beam intensity.
To properly display ECG trace and characters, the clock rate is changed
and the analog deflection filters are switched. The clock rate (OCLK) is
controlled with the two high order bits of the intensity byte (EXTR1 and
EXTR2)
to
provide
4
MHz
for
character
and
2
MHz
for
ECG
trace.
The
filter selections are controlled by the attribute bit (EXTR3).
IV-12