Zynq UltraScale+ User Manual

RFSoC Data Converter Evaluation Tool User Guide 18
UG1287 (v2018.2) October 1, 2018 www.xilinx.com
Chapter 3: Hardware Design
Figure 3-5 shows the TREADY signal generation. Only a single TREADY signal is selected
based on the Channel Select signal; other TREADY signals are ignored.
X-Ref Target - Figure 3-4
Figure 3-4: Channel Selection Control Signals
Tvalid 0..7
Memory
Loopback
0
Memory
Loopback
1
------------
Memory
Loopback
7
Channel Select 0..7
Channel Arbiter
X21236-092118
X-Ref Target - Figure 3-5
Figure 3-5: TREADY Signal Generation
Memory Loopback
0
Memory Loopback
1
------------
Memory Loopback
7
Mux
TReady
Channel Arbiter
X21237-092118
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Zynq UltraScale+ Specifications

General

Max Transceivers	Up to 32
Transceiver Speed	Up to 32.75 Gbps
Family	Zynq UltraScale+
Processor Cores	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
Max Memory	DDR4
Power Consumption	Varies by configuration, typically 10W to 30W
Operating Temperature	Industrial (-40°C to +100°C), Extended (-40°C to +125°C)
Package Options	Various BGA packages
Category	FPGA SoC