COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 6 Copyright © 2023 ADLINK Technology, Inc.
- Lane polarity inversion
- 5x PCIe_REFCLK/PCIe_CLKREQ
PCIe_REFCLK0_LO & PCIe_CLKREQ0_LO# : for PCIe lanes [0:7] and PCIe_BMC
PCIe_REFCLK0_HI & PCIe_CLKREQ0_HI# : for PCIe lanes [8:15]
PCIe_REFCLK1 & PCIe_CLKREQ1# : for PCIe lanes [16:31]
PCIe_REFCLK2 & PCIe_CLKREQ2# : for PCIe lanes [32:47]
PCIe_REFCLK3 & PCIe_CLKREQ3# : for PCIe lanes [48:63]
Note: Due to SoC orientation, the trace of PCIe 48-63 lanes over the PICMG specification marginally and may require re-driver on carrier.
PCI Express Dedicated for Carrier BMC
1x PCIe lane (called PCIe_BMC)
They can be used to connect the Carrier BMC (located on carrier) and combined with MMC (Module Management Controller, build option feature), such
as voltage monitoring, power on/off, in the server applications.
Boot SPI
1x Boot_SPI, 2x Boot_SPI_CS dedicated for boot BIOS flash usage
SPI clock is either 20 MHz, 25 MHz, 33 MHz (Ampere Altra SOC only support up to 30MHz)
Support 3.3V of VCC_BOOT_SPI pin, if SPI flash on carrier is implemented, it shall be powered by VCC_BOOT_SPI pin
BIOS Boot Selection
BIOS flash can be boot up at SPI bus, can be located at module or carrier or combined
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