ADLINK Technology arm AMPERE COM-HPC-ALT - Port 80 Support on USB_PD I2 C Bus; Ipmb

COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
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Name
Pin #
Description
I/O
PU / PD
Comment
I2C0_CLK
A30
Clock I/O line for the general purpose I2C0 port
I/O OD
3.3VSB
PU 2K2
3.3VSB
I2C0_DAT
A29
Data I/O line for the general purpose I2C0 port
I/O OD
3.3VSB
PU 2K2
3.3VSB
I2C0_ALERT#
A32
Alert input / interrupt for I2C0
I 3.3V
PU 2K2
3.3VSB
I2C1_CLK
A33
Clock I/O line for the general purpose I2C1 port
I/O OD
1.8VSB
PU 2K2
1.8VSB
I3C Not supported
I2C1_DAT
B28- B30
Data I/O line for the general purpose I2C1 port
I/O OD
1.8VSB
PU 2K2
1.8VSB
I3C Not supported
Note: multi-master support is I2C0 and I2C1
Supports 100KHz, 400KHz, and 1MHz
4.3.7 Port 80 Support on USB_PD I2C Bus
COM-HPC Module should support exporting Port 80 information over the USB_PD I2C bus (signals USB_PD_I2C_DAT and USB_PD_I2C_CLK) (pin B36 and
B35) to Carrier hardware that implements a pair of 7-segment displays to show the codes.
4.3.8 IPMB
An IPMB (Intelligent Platform Management Bus) port is defined for both the Client and Server pinout types for platform management functions. The
IPMB is used (optionally) with a Carrier based BMC (Board Management Controller) Master. On the Module, the IPMB should be routed to and used