COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 17 Copyright © 2023 ADLINK Technology, Inc.
COM-HPC Carrier Board EEPROM
The Carrier Board should implement a serial EEPROM that identifies the Carrier using the Unique Device Id and describes the expected PCI Express link
configuration. In addition this EEPROM may describe the expected link presence for SATA, USB, DDI, VGA, LAN, audio, and the expected presence of
miscellaneous I/O signals. The EEPROM may be implemented as a physical EEPROM on the board, or may be realized within the BMC (see Section
Error! Bookmark not defined.).
The Carrier EEPROM allows the Module firmware to set up any software configurable Module features in a way that is appropriate for the Carrier Board.
If there is an incompatibility between the expected Carrier Board configuration and the Module capabilities, an error message may be generated. The
error messaging is Module vendor specific and is not defined by this standard.
The Carrier EEPROM device address lines, A2, A1 and A0 shall be pulled to a logic high, placing the device at address 0x57 (7 bit addressing) and 0xAE(8
bit addressing). I2C addresses A6-A3 are fixed at 1010b for I2C EEPROM devices.
2.8 Debug
40 pin flat cable connector to be used with DB40 HPC debug module
Supports BIOS POST code LED, BMC access, SPI BIOS flashing, internal power rail test points, debug LEDs
2.9 Power
Power Modes: AT and ATX mode
Standard Voltage Input: ATX 12V±5% / 5Vsb ±5% or AT 12V±5%
Power Management: ACPI 5.0 compliant, Smart Battery support
Power States: C1-C6, S0, S1, S5, S5 ECO mode (Wake-on-USB, WoL S5)
ECO Mode support for deep S5 for 5Vsb power saving
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