ADLINK Technology arm AMPERE COM-HPC-ALT - Signal Descriptions on J1;J2 Connectors

COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 8 Copyright © 2023 ADLINK Technology, Inc.
4.3 Signal Descriptions on J1/J2 Connectors
4.3.1 Ethernet KR/KX
Ethernet KR interface are defined for COM-HPC. For these ports, the Ethernet MACs are located on COM-HPC module. PHYs (if used) are on the Carrier.
In some cases, no PHY is required, for short cable (“Direct Attach” cables) or Carrier runs.
COM-HPC support both of MDIO and I2C control interfaces for the PHYs. The MDIO and I2C control interfaces are grouped into quads, for KR ports 0:3
and ports 4:7
Name
Pin #
Description
I/O
PU / PD
Comment
ETH0_TX-
ETH0_TX+
ETH1_TX-
ETH1_TX+
ETH2_TX-
ETH2_TX+
ETH3_TX-
ETH3_TX+
C20
C21
C23
C24
C26
C27
C29
C30
Ethernet KR ports, transmit output differential pairs.
O
KR
AC coupled Off Module
ETH0_RX-
ETH0_RX+
ETH1_RX-
ETH1_RX+
ETH2_RX-
ETH2_RX+
ETH3_RX-
ETH3_RX+
D19
D20
D22
D23
D25
D26
D28
D29
Ethernet KR ports, receive input differential pairs.
I
KR
AC coupled Off Module
ETH0-3_MDIO_DAT
H99
Management Data I/O interface mode data signal for
serial data transfers between the MAC and an
external PHY for ETHx ports 0 to 3
I/O
3.3VSB
PU 2K2
ETH0-3_MDIO_CLK
H98
Clock signal for Management Data I/O interface
mode data signal for serial data transfers between the
MAC and an external PHY for ETHx ports 0 to 3
O
3.3VSB
ETH0-3_INT#
G99
Active low interrupt signal from IO Port expanders for
ETH ports 0 to 3
I
3.3VSB
PU 2K2