COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 8 Copyright © 2023 ADLINK Technology, Inc.
General Purpose SPI
1x GP_SPI, 2x GP_SPI_CS
A TPM is located on GP_SPI bus
SM Bus
1x SMBus comes from SoC I2C_9 bus
2.3 Ethernet
NBASE-T Ethernet
Intel® Ethernet Controller i210/i211, connected to the SoC through PCIe lane
Supports 10/100/1000 Mbps data transfer rates, both full-duplex and half-duplex
Supports NBASET_SDP, Software-Defined Pin. Can also be used for IEEE 1588 support such as 1pps signal
Supports Wake on LAN at S3/S4/S5
Supports PXE boot
Ethernet KR/KX Interfaces
Broadcom® Ethernet Controller BCM57502, connected to the SoC through PCIex8 lane
4x 10GBASE-KR and its sideband signals
Supports both full-duplex and half-duplex
To Next Page
Loading...
