ADLINK Technology arm AMPERE COM-HPC-ALT - NBASE-T Ethernet

COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 9 Copyright © 2023 ADLINK Technology, Inc.
ETH0-3_PHY_INT#
G98
Active low PHY interrupt signal from ETH ports 0 to 3
I
3.3VSB
PU 2K2
ETH0-3_PHY_RST#
F97
Active low output PHY reset signal for ETH ports 0 to
3.
O
3.3VSB
ETH0-3_I2C_DAT
G97
I2C data signal of the 2-wire management interface
used by the Ethernet KR controller to access the
management registers of an external SFP Module or
to configure the Carrier PHY for ETHx ports 0 to 3 and
for serialized status information (e.g. LED states)..
I/O OD
3.3VSB
PU 2K2
ETH0-3_I2C_CLK
G96
The I2C clock signals associated with ETH0-3 I2C data
lines in the row above.
I/O OD
3.3VSB
PU 2K2
ETH0_SDP
ETH1_SDP
ETH2_SDP
ETH3_SDP
F98
F99
F1
F2
Software-Definable Pins. Can also be used for
IEEE1588 support such as a PPS signal.
I/O
3.3VSB
ETH0-3_PRSNT#
H96
Carrier pulls this line to GND if there is Carrier
hardware present to support Ethernet KR signaling on
ETH0 through ETH3. If the entire KR quad is not
supported it should fill from ETH0 on up.
I
3.3VSB
PU
Note: The Ethernet KR support is 10GBASE-KR
4.3.2 NBASE-T Ethernet
The port may operate in 10Gbps, 5Gbps, 2.5Gbps, 1Gbps, 100Mbps, or 10Mbps modes. Magnetics are to be on the Carrier board. The COM-HPC
module shall be capable of 1000BASE-T mode.
Name
Pin #
Description
I/O
PU / PD
Comment
NBASET0_MDI0-
D85
D86
Ethernet Controller 1: Media Dependent Interface Differential Pairs
0,1,2,3. The MDI can operate in 10Gbps, 1Gbps, 100Mbps and 10
I/O Analog
Twisted pair signals for external transformer.