ADLINK Technology arm AMPERE COM-HPC-ALT - Page 46

COM-HPC-ALT User’s Guide PICMG COM-HPC R1.0
Page 17 Copyright © 2023 ADLINK Technology, Inc.
PCIe50_RX+
PCIe50_RX-
PCIe51_RX+
PCIe51_RX-
PCIe52_RX+
PCIe52_RX-
PCIe53_RX+
PCIe53_RX-
PCIe54_RX+
PCIe54_RX-
PCIe55_RX+
PCIe55_RX-
PCIe56_RX+
PCIe56_RX-
PCIe57_RX+
PCIe57_RX-
PCIe58_RX+
PCIe58_RX-
PCIe59_RX+
PCIe59_RX-
PCIe60_RX+
PCIe60_RX-
PCIe61_RX+
PCIe61_RX-
PCIe62_RX+
PCIe62_RX-
PCIe63_RX+
PCIe63_RX-
F75
F74
F78
F77
F81
F80
F84
F83
F87
F86
F90
F89
G70
G69
G73
G72
G76
G75
G79
G78
G82
G81
G85
G84
G88
G87
G91
G90
PCIe_BMC_TX-
PCIe_BMC_TX+
A59
A60
PCI Express Differential Transmit Pair for Carrier BMC
(Board Management Controller)
O PCIe
AC coupled on Module
PCIe_BMC_RX-
PCIe_BMC_RX+
B58
B59
PCI Express Differential Transmit Pair for Carrier BMC
(Board Management Controller)
I PCIe
AC coupled off Module
PCIe_REFCLK0_LO-
PCIe_REFCLK0_LO+
C59
C60
Reference clock pair for PCIe lanes [0:7], also referred
to PCIe Group 0 Low and for the PCIe_BMC link
O PCIe
PCIe_REFCLK0_HI-
PCIe_REFCLK0_HI+
C57
C56
Reference clock pair for PCIe lanes [8:15], also
referred to PCIe Group 0 High
O PCIe