Agilent Technologies 33120A - Page 266

. . . continued
void rst_clear(void)
{
/* Reset the function generator, clear the error queue, and wait for
commands to complete. A "1" is sent to the output buffer from the
*OPC? command when *RST and *CLS are completed. */
float value;
IOOUTPUTS(ADDR, "*RST;*CLS;*OPC?", 15);
IOENTER(ADDR, &value);
}
/**************************************************************************/
void setup_status(void)
{
/* An interrupt is to be generated whenever an error is detected.
To enable the status registers to generate an interrupt, you must
enable bits in the Status Byte and Standard Event Register. */
/* Enable bit 5 "Standard Event" in the Status Byte to recognize
activity from the Standard Event Register (2^5 = 32) */
IOOUTPUTS(ADDR, "*SRE 32", 7);
/* Enable bits 2, 3, 4, and 5 in the Standard Event Register to
interrupt the Status Byte (2^2 + 2^3 + 2^4 + 2^5 = 60) */
IOOUTPUTS(ADDR, "*ESE 60", 7);
}
/**************************************************************************/
Chapter 6 Application Programs
Using the Status Registers
264