50 Agilent 35670A Supplement
4 Service Guide
A101 Display
The following table lists signals routed between the A17 board
and the LCD display assembly. All signals are generated on the
A17 board and are used by the display assembly. A description
of each signal follows the table. All data lines are LVDS.
CLK: LVDS pair carrying the 66.660MHz clock signal used by the
LCD screen
Pixel Data 2: LVDS pair carrying blue pixel bits 4 to 7, Hsync,
Vsync, and Data enable signals
Pixel Data 1: LVDS pair carrying green pixel bits 3 to 7, and blue
pixels bits 2 to 3
Pixel Data 0: LVDS pair carrying red pixel bits 2 to 7, and green
pixels bit 2.
VCC: 3.3 Volts.
Page in original guide 9-36
CLK + 6
CLK – 7
Pixel Data 2 + 9
Pixel Data 2 – 10
Pixel Data 1 + 12
Pixel Data 1 – 13
Pixel Data 0 + 15
Pixel Data 0 – 16
VCC 19,20
Gnd 1,2,3,4,5,8,11,14,17,18