Theory of Operation 4
E4416A/E4417A Power Meters Service Guide 83
The output of the equalizer is split into two paths. One path is amplified by a
gain of 100. Both signals are each converted to digital words by a dual analog
to digital converter (ADC). The ADC's sampling rate has an integer
relationship with the chop frequency, thus giving a fixed number of samples
per chop cycle.
In the event of a power overload- which could cause the input amplifier to
saturate- a window comparator function trips which generates an interrupt to
the processor assembly through the FPGA. The FPGA also forces the sensor
into upper range using the I2C_NEN line.
The ADC uses an I2S interface into the DSP where the samples are
de- chopped and converted into digital words proportional to input level. The
chosen channel is then filtered and stored in a buffer ready for reading by the
host processor.
An analogue switch is used to inject a calibration into this path to allow
calibration of the gain ratio between the two ranges.
Normal Path
The second path, or normal path, deals with peak mode measurements. Here
the input signal is the detected power envelope of the RF input to the sensor.
The E9320- Series sensor detects this and, for peak mode measurements,
amplifies it as a fully differential voltage signal with a bandwidth from DC to 5
MHz. The normal path processes the output of an E9320- Series sensor and
converts it to a form suitable for digitizing in a 12 bit ADC), at a rate of 20 M
samples/sec. The sensor has a 50 Ω source impedance for each of the
differential lines, the sensor cable has a differential impedance of 100 Ω and
the measurement card has a 100 Ω load impedance at the input to the first
amplifier. The purposes of the first amplifier are to buffer the input signal, to
allow offset control and to drive the anti- alias filter. Offset control comes from
the main processor via a DAC into the first amplifier and a feedback control
algorithm carried out during zeroing ensures that gross voltage offsets are
nulled out before reaching the ADC.
The offset- corrected amplifier output is then filtered. The filter is a
differential implementation of a 9th order Bessel low- pass filter, designed for
a flat delay of approximately 100ns, a 3 dB bandwidth of approximately 5 MHz
and 22 dB attenuation at 15 MHz.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
To Next Page
Loading...
Need help?
General
