Alinx AXKU040 - Page 50

KINTEX UltraScale+ FPGA Board AXKU040 User Manual
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SMA_RX_N
MGTHRXN3_225
AB1
Transceiver Signal Input
The schematic diagram of FPGA and SATA interface connection is shown
in Figure 12-2.
Figure 12-2: SATA Connection Schematic
SATA Interface pin assignment:
Signal Name
FPGA Pin
FPGA Pin
Number
Description
SATA1_ TX_P
MGTHTXP0_225
AH6
SATA1 Data Transmission P
SATA1_ TX_N
MGTHTXN0_225
AH5
SATA1 Data Transmission N
SATA1_ RX_P
MGTHRXP0_225
AH2
SATA1 Data Receive P
SATA1_ RX_N
MGTHRXN0_225
AH1
SATA1 Data Receive N
SATA2_ TX_P
MGTHTXP1_225
AG4
SATA2 Data Transmission P
SATA2_ TX_N
MGTHTXN1_225
AG3
SATA2 Data Transmission N
SATA2_ RX_P
MGTHRXP1_225
AF2
SATA2 Data Receive P
SATA2_ RX_N
MGTHRXN1_225
AF1
SATA2 Data Receive N